EN0-001 ARM Accredited Engineer Questions and Answers

1 byte

2 bytes

4 bytes

8 bytes

Accessing a large memory device consumes less power than accessing a small one

A series of non-sequential accesses is more efficient than a series of sequential accesses

Increasing the size of the cache will always reduce power consumption for a given application

Storing frequently used data in Tightly Coupled Memory will reduce power consumption

Instruction cache clean only

Instruction cache invalidate only

Data cache clean and instruction cache invalidate

Data cache invalidate and instruction cache invalidate

The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory

Secure memory contents are encrypted, and cannot be decrypted by Non-secure software

The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set

The MMU generates an abort on accesses to Secure memory performed by Non-secure software

It allows a complete trace of real-time program execution to be captured

It reduces the number of pins required to connect the debugger to the processor

It allows examination of the system state before and after execution of a statement

It requires only one change to the program source code

The Call Stack view

The Memory view

The Registers view

The Variables view

DSBSY

DSBST

DMBSY

DMBST

Disabling inlining.

Never passing more than four parameters in function calls.

Declaring automatic variables as " packed " .

Configuring the compiler to optimize for space.

After instruction A and before the DSB

After the DSB and before instruction B

After instruction B and before instruction C

After instruction C and before instruction D

The Clocks Per Instruction (CPI) of the processor has increased

The processor is NOT the limiting factor on performance

Instruction cache utilization has improved

The core has stopped carrying out speculative data memory accesses

Only 16-bit Thumb instructions.

Only 32-bit Thumb instructions.

16-bit and 32-bit Thumb instructions.

32-bit Thumb and certain ARM instructions.

Produce a binary object that will run on processors based on any architecture.

Mix different source languages within the same source file and compile with a single tool.

Run code written for one processor on a processor based on a different architecture.

Compile target code using a computer based on a different architecture.

5 cycles

7 cycles

8 cycles

15 cycles

Functions that are not compliant with the ISO C library standard

Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic

Target-dependent functions which use semihosting

Functions called implicitly by the compiler

Encrypts Secure register contents, sets the NS bit in SCTLR and branches directly to Normal world code

Saves Secure register contents, sets all registers to zero, sets the NS bit in SCTLR and branches directly to Normal world code

Saves Secure register contents, loads Non-secure ones from memory, sets the NS bit in SCTLR and performs an exception return

Sets the NS bit in SCTLR and performs an exception return - all registers are banked in hardware and switched automatically

Inactive

Active

Pending

Edge-triggered

Influenced by breakpoints.

Intrusive on normal processor operation.

Inaccurate regarding code execution history.

Not intrusive on normal processor operation.

Produce faster code.

Produce smaller code.

Produce non standard-compliant code.

Produce code that might be easier to debug.

An external DMA engine modifies data in a region of data memory which is already cached by the processor

An external agent needs to read data which has been modified by the processor in a cacheable memory region

Debugger reads data from a shared, cacheable memory location

One core modifies data in a shared cacheable memory region

Copying data from Flash to RAM

Changing from one privileged mode to another

Loading code into memory and then executing it

Incrementing a RAM location that will be read by an interrupt handler

LDR r0, [r0], #1

LDR r0, [r0]. #4

LDR r0, [r0.#1]

LDR r0, [r0. #4]

PC interface hardware for configuring a boot monitor

Hardware specific source code needed for operating system support

A working port of Linux for a specific hardware platform

Debugging hardware and software supplied with a development board

It must start executing from RAM

RAM must be initialized before reset

Exception handlers must execute from ROM or flash memory

It must not execute semihosting SVC or BKPT instructions

Stack

Heap

Registers

Hard disk

Use an ETM instruction trace profiler, which outputs information about the program as it runs

Add some serial logging to the software, which outputs information about the program as it runs

Add a new interrupt handler, which is triggered off a timer, and dump information about the interrupted process

Use a JTAG sample-based profiler, which periodically halts the CPU, and dumps information about the interrupted process

Hard floating-point linkage

Soft floating-point linkage without floating-point hardware

Hard floating-point linkage with optimization for space

Soft floating-point linkage with floating-point hardware

Current Program Status Register (CPSR)

Contents of the Level 2 data cache

The Floating Point Status and Control Register (FPSCR)

All User mode general-purpose registers

The CP15 Multiprocessor Affinity Register

Contents of the Level 1 data cache

Replace all functions which use semi-hosting

Locate the stack in an area of RAM

Set the locale variable appropriately

All functions in the standard library must be rewritten

a- > s0; b- > d0; c- > s1

a- > s0; b- > d1; c- > s1

a- > d0; b- > d1; c- > d2

a- > s0; b- > d1; c- > s2

0x11223344

0x44332211

0x22114433

0x33441122

Memory mapping

Semihosting

Polling

Virtual I/O

This transition is not possible

Execution of an SMC instruction

Execution of an SMC instruction followed by an SVC instruction

Execution of an SVC instruction followed by an SMC instruction

The memory contents could be set to zero

Some memory contents could be rewritten

The processor MMU pagetables could be modified

The processor cache could be cleaned or/and invalidated

A function must preserve R0-R3 and R12

A function must preserve R4-R11 andR13

No registers may be corrupted by any function

All registers may be corrupted by any function

0x80003FF8

0x80004000

0x80004008

R1 contents are unpredictable

19

20

24

28

A dual-core Cortex-A9 processor

A Cortex-R4 processor with a Cortex-M3 system controller

A Cortex-A8 processor with a graphics processing unit (GPU)

A uni-core Cortex-A5 processor with a digital signal processor (DSP)

Put the processor(s) into debug state.

Force the processor to execute a BKPT instruction

Hold the processor in a Reset condition

Re-initialize the memory contents.

Storage can be easily replaced, for example to increase capacity.

It is quicker to access, providing far greater bandwidth for read operations.

It has a longer life, indicated by being rated for a higher number of write cycles.

It takes up less physical space in a device, and does not require any space on the printed circuit board.

The exception vector table

The Memory Management Unit (MMU) translation table

The Stack Pointer (SP)

The System Control Register (SCTLR)

It traps writes to the memory containing the vector table

It provides additional resources for debugging exception handlers

It provides configurable exception priorities on an ARM processor

It provides an improved mechanism for an application to handle exceptions

In system memory

In registers shared with the VFP register set

In registers shared with the integer register set

In dedicated registers not shared with other registers

8 bits

16 bits

32 bits

64 bits

None

Always one

Always three

One or more depending on optimization level

P1 = 0x0F, P2 = 0x10, PM = 0xFF

P1 = 0x10, P2 = 0x0F, PM = 0xFF

P1 =0x0F, P2 = 0x10. PM = 0x0

P1 = 0x10, P2 = 0x0F, PM = 0x0

By executing an SGI instruction

By writing to a register in the GIC

By writing to the F bit in the CPSR

By writing to the I bit in the CPSR

The MMU uses translation tables. The MPU does not use translation tables.

The MMU uses only physical addresses. The MPU translates virtual addresses to physical addresses.

The MMU defines cacheability attributes for memory. The MPU does not define cacheability attributes for memory.

The MMU defines access permissions for memory. The MPU does not define access permissions for regions of memory.

Tracing using Embedded Trace Macrocell (ETM)

Halt mode debugging

Monitor mode debugging

Using the Performance Monitor Unit

Abort mode

System mode

Hypeivisor mode

Supervisor mode

The library directly sends I/O requests to the debugger using the JTAG connection

While the target is running, the debugger processes I/O requests from a shared queue in memory

The I/O library calls rely on an Ethernet connection to redirect the requests to the debugger

The I/O library calls generate an exception that is trapped and handled by the debugger

200

201

204

208

Core register contents

CP15 (system) register settings

Debug state

Cache contents

Ensuring constants can be encoded as immediates in the current instruction set.

Storing the code in ROM.

Using Thumb code rather than ARM code.

Compiling and linking as position-independent code.

Registers R0-R15

Thread and process ID registers

The CPSR

NEON and VFP registers

NEON (Advanced SIMD)

Thumb-2 technology

TrustZone (Security Extensions)

Generic Interrupt Controller

Observe changes to a local variable in a function

Capture a real-time trace of program execution

Debug boot code, before a call to the C main() function

Stop the processor at an interesting location in the code

__package

__packed

__compact

__compress

Protect memory.

Improve performance.

Implement virtual memory,

Ensure correct ordering of memory operations.

Register an interrupt which is triggered when the counter overflows

Count the events using a 64-bit VFP register

Allow one event type to use concatenated counter registers

Poll the event counter, resetting it when the counter is close to overflowing

0x00000000

0xFFFFFFFF

0x11111111

0xAAAAAAAA